Non-volatile memory devices, such as flash memory devices, store data in cells. The cells generally comprise semiconductor material configured to allow the cell to be placed in a particular state and allow that state to be read at a later time. For example, a cell having two states (e.g., 0 and 1) may be placed in a particular state by iteratively applying a programming voltage across the cell. At a later point in time, a reading voltage may be applied to the cell and the resulting current across the cell may be determined to determine the state of the cell. The reading voltage may be greater than the threshold voltage for one state and less than the threshold voltage for the other state. If the current resulting from the applied reading voltage is low or approximately zero, it is determined that the cell is in one state and if the current is not low, than it is determined that the cell is in the other state. Multi-level cells (e.g., cells having more than two states) are also known and commonly used.
When a number of cells are combined to form a memory device or a memory chip, coupling between cells can occur. For example, cell-to-cell interference, such as bit line interference has been attributed to a parasitic capacitance coupling effect in which the threshold voltage of one cell is changed by a shifting the threshold voltage of a neighboring cell. This may cause the victim or attacked cell to be over programmed or placed in the wrong state.
Various attempts to reduce bit line interference have been made. These attempts focus on topology tuning such as including an air-gap or a deeper control gate plug between field gates. However, too deep a control gate plug or a non-uniform air-gap will degrade cell reliability and performance.
Therefore, there is a need in the art for methods, devices, and/or the like for reducing bit line interference. In particular, there is a need in the art for methods, devices, and/or the like for reducing bit line interference without degrading cell reliability and performance.